Japan, Sept. 18 -- GSEC CO LTD has got intellectual property rights for 'CONFIGURATION METHOD OF LOGIC CIRCUIT USING PHOTORELAY, LOGIC CIRCUIT USING PHOTORELAY, LOGIC CIRCUIT SIMULATOR, AND PROGRAM.' Other related details are as follows:
Application Number: JP,2025-077883
Category (FI): H03K17/78@K,H03K19/20
Stage: PROBLEM TO BE SOLVED: To provide a logic circuit using a photorelay having high reliability.SOLUTION: A logic circuit includes a first resistance group and a second resistance group consisting of resistances according to the input of a logic function, and supplies a power supply voltage to one terminal on the input side of a photorelay through the resistance of the first resistance group in response to an input with a logic value of 1 of the logic function, and the resistance of the second resistance group is grounded via the resistance in response to an input where the logic value of the logic function is 0, a resistance network is configured to be connected in parallel between both terminals on the input side of the photorelay, and the resistance network is configured on the basis of a threshold logic function such that a logic value corresponding to an input of the logic function becomes a conduction function on the output side of the photorelay.SELECTED DRAWING: Figure 2 (Grant)
Filing Date: May 8, 2025
Publication Date: July 10, 2025
The original document can be viewed at: https://www.j-platpat.inpit.go.jp/p0100
Disclaimer: Curated by HT Syndication.
