Japan, March 5 -- TOSHIBA ELECTRONIC DEVICES & STORAGE CORP,TOSHIBA CORP has got intellectual property rights for 'SEMICONDUCTOR DEVICE.' Other related details are as follows:

Application Number: JP,2022-045873

Category (FI): H01L29/78,658@A,H01L29/78,652@P,H01L29/86,301@F,H01L29/86,301@E,H01L29/86,301@D,H01L29/78,652@T,H01L29/78,655@F,H01L29/78,652@F,H01L29/78,652@S,H01L29/06,301@G,H01L29/06,301@V,H01L29/91@K,H10D8/50@K,H10D8/60@F,H10D8/60@E,H10D8/60@D,H10D12/00,101@F,H10D12/00,101@T,H10D12/00,103,H10D12/01@A,H10D62/10,101@G,H10D62/10,101@V,H10D12/00,103@C,H10D30/66,101@T,H10D30/66,103@C,H10D12/00,103@B,H10D12/00,103@S

Stage: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving a withstanding voltage of a termination region surrounding an active region to enhance a withstanding voltage of the semiconductor device.SOLUTION: A semiconductor device 1 has: a first semiconductor layer 11 of a first conductivity type that has an active region AR and a termination region TR surrounding the active region; a first electrode 20; a second electrode 30 provided in the active region so that the first semiconductor layer is located between the first electrode and itself; a second semiconductor layer 13 of a second conductivity type provided between the first semiconductor layer and the second electrode, and having a first layer thickness in a first direction from the first electrode toward the second electrode; a third semiconductor layer 15 of the second conductivity type provided in the termination region so as to surround the second semiconductor layer, and having a second layer thickness larger than the first layer thickness in the first direction; a fourth semiconductor layer 17 of the second conductivity type that surrounds the second and third semiconductor layers, and having a third layer thickness smaller than the second layer thickness in the first direction; and a fifth semiconductor layer 19 of the second conductivity type provided so that the third and fourth semiconductor layers are located between the first semiconductor layer and itself.SELECTED DRAWING: Figure 1 (Grant)

Filing Date: March 22, 2022

Publication Date: Oct. 4, 2023

The original document can be viewed at: https://www.j-platpat.inpit.go.jp/p0100

Disclaimer: Curated by HT Syndication.